Linaro Snapshots

Name	Last modified	Size	License

Parent Directory
gcc-linaro-snapshot-5.2-2015.11.tar.xz	15-Jan-2018 17:40	73.3M	open
gcc-linaro-snapshot-5.2-2015.11.tar.xz.asc	15-Jan-2018 17:40	73	open

Release Notes

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.11 snapshot of the Linaro GCC 5 source package.

This monthly snapshot¹ is based on FSF GCC 5.2+svn230068 and includes performance improvements and bug fixes backported from mainline GCC. This snapshot contents will be part of the 2015.11 stable [1] quarterly release.

Interesting changes in this GCC source package snapshot include:

Updates to GCC 5.2+svn230068
Backport of [Bugfix] [AArch32] fp16 Fix PR 67624 – Incorrect conversion of float Infinity to __fp16
Backport of [Bugfix] [AArch64] PR 66776 Add cmovdi_insn_uxtw pattern
Backport of [Bugfix] [AArch64] PR rtl-optimization/68106 LRA
Backport of [Bugfix] PR48052 fix testcase
Backport of [Bugfix] PR other/57195
Backport of [Bugfix] PR rtl-optim/67421 Cost instruction sequences when doing left wide shift
Backport of [Bugfix] PR rtl-optimization/67103 Improve conditional select ops on immediates
Backport of [Bugfix] PR rtl-optimization/67756
Backport of [Bugfix] PR target/61578
Backport of [Bugfix] PR target/61578
Backport of [Bugfix] PR target/61578
Backport of [Bugfix] PR tree-optimization/48052 IVOPTS
Backport of [Bugfix] PR tree-optimization/52563 and 62173 IVOPTS
Backport of [Bugfix] PR tree-optimization/64454
Backport of [Bugfix] PR tree-optimization/66449
Backport of [AArch32] 1/2 Record FPU features as a bit-set
Backport of [AArch32] 2/2 Use new FPU features representation
Backport of [AArch32] 1/5 Make room for more CPU feature flags
Backport of [AArch32] 2/5 Add feature set definitions
Backport of [AArch32] 3/5 Use new feature set representation
Backport of [AArch32] 4/5 Use features sets for builtins
Backport of [AArch32] 5/5 Move initializer into arm-cores.def and arm-arches.def
Backport of [AArch32] Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)_insn rtx pattern
Backport of [AArch32] Add missing is_neon_type types
Backport of [AArch32] arm memcpy of aligned data
Backport of [AArch32] Fix arm bootstrap failure due to -Werror=shift-negative-value
Backport of [AArch32] fix vget_lane on big-endian
Backport of [AArch32] Use %wd format for lane printing in bounds_check
Backport of [AArch32/AArch64] 1/15 [FP16] Hide existing float16 intrinsics unless we have a scalar __fp16 type
Backport of [AArch32/AArch64] 2/15 [fp16] float16×4_t intrinsics in arm_neon.h
Backport of [AArch32/AArch64] 3/15 Add V8HFmode and float16×8_t type
Backport of [AArch32/AArch64] 4/15 float16×8_t intrinsics in arm_neon.h
Backport of [AArch32/AArch64] 5/15 Remaining intrinsics
Backport of [AArch32/AArch64] 6/15 Add basic FP16 support
Backport of [AArch32/AArch64] 8/15 Add support for float16x{4,8}_t vectors/builtins
Backport of [AArch32/AArch64] 9/15 vld{2,3,4}{,_lane,_dup}, vcombine, vcreate
Backport of [AArch32/AArch64] 10/15 Implement vcvt_{,high_}f16_f32
Backport of [AArch32/AArch64] 11/15 vreinterpret(q?), vget_(low|high), vld1(q?)_dup
Backport of [AArch32/AArch64] 12/15 Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix
Backport of [AArch32/AArch64] 13/15 Add float16 tests to advsimd-intrinsics testsuite
Backport of [AArch32/AArch64] 14/15 Add test of vcvt{,_high}_i{f32_f16,f16_f32}
Backport of [AArch32/AArch64] 15/15 Update sourcebuild.texi with testsuite/effective-target hooks
Backport of [AArch64] 1/5 Reimplement aarch64_bitmask_imm
Backport of [AArch64] 2/5 Improve aarch64_internal_mov_immediate by using faster algorithm
Backport of [AArch64] 3/5 Remove dead code
Backport of [AArch64] 4/5 Remove redundant code
Backport of [AArch64] 5/5 Cleanup immediate generation code in aarch64_internal_mov_immediate
Backport of [AArch64] 1/14 Add ident field to struct processor
Backport of [AArch64] 2/14 Refactor arches handling, add arch enum identifier
Backport of [AArch64] 3/14 Refactor option override code
Backport of [AArch64] 4/14 Create TARGET_FIX_ERR_A53_835769 and use that instead of aarch64_fix_a53_err835769
Backport of [AArch64] 5/14 Make flag_omit_leaf_frame_pointer intialize to 2. Define and use TARGET_OMIT_LEAF_FRAME
Backport of [AArch64] 6/14 Implement TARGET_OPTION_SAVE/TARGET_OPTION_RESTORE
Backport of [AArch64] 7/14 Implement TARGET_SET_CURRENT_FUNCTION
Backport of [AArch64] 8/14 Implement TARGET_OPTION_VALID_ATTRIBUTE_P
Backport of [AArch64] 9/14 Implement TARGET_CAN_INLINE_P
Backport of [AArch64] 10/14 Implement target pragmas
Backport of [AArch64] 11/14 Re-layout SIMD builtin types on builtin expansion
Backport of [AArch64] 12/14 Target attributes and target pragmas tests
Backport of [AArch64] 13/14 Document AArch64 target attributes and pragmas
Backport of [AArch64] 14/14 Reuse target_option_current_node when passing pragma string to target attribute
Backport of [AArch64] vtbl³⁴ and vtbx4
Backport of [AArch64] Add backend aarch64_bfi pattern
Backport of [AArch64] Add csneg3_uxtw_insn pattern
Backport of [AArch64] Add support for 64-bit vector-mode ldp/stp
Backport of [AArch64] Adjust tests to take LSE extension into account
Backport of [AArch64] [array_mode 1/8] Rename vec_store_lanes_lane to aarch64_vec_store_lanes_lane
Backport of [AArch64] [array_mode 2/8] Remove VSTRUCT_DREG, use BLKmode for d-reg aarch64_st/ld expands
Backport of [AArch64] [array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md
Backport of [AArch64] [array_mode 4/8] Remove EImode
Backport of [AArch64] [array_mode 5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size.
Backport of [AArch64] [array_mode 6/8] Remove V_TWO_ELEM, again using BLKmode + set_mem_size.
Backport of [AArch64] [array_mode 7/8] Combine the expanders using VSTRUCT:nregs
Backport of [AArch64] [array_mode 8/8] Add d-registers to TARGET_ARRAY_MODE_SUPPORTED_P
Backport of [AArch64] Break -mcpu tie between the compiler and assembler
Backport of [AArch64] [expand] Check gimple statement to improve LSHIFT_EXP expand
Backport of [AArch64] Fix FAIL: gcc.target/aarch64/target_attr_crypto_ice_1.c (internal compiler error)
Backport of [AArch64] Fix vcvt_high_f64_f32 and vcvt_figh_f32_f64 intrinsics
Backport of [AArch64] Fix vldX/vstX AdvSIMD intrinsics
Backport of [AArch64] Followup to [AArch64_be] Fix vtbl³⁴ and vtbx4
Backport of [AArch64] Force __builtin_aarch64_fp[sc]r argument into a REG
Backport of [AArch64] Handle const address in aarch64_print_operand
Backport of [AArch64] Implement copysign[ds]f3
Backport of [AArch64] Improve code generation for float16 vector code
Backport of [AArch64] Improve SIMD concatenation with zeroes
Backport of [AArch64] Remove index from AARCH64_FUSION_PAIR
Backport of [AArch64] Remove obsolete comment in aarch64-option-extensions.def
Backport of [AArch64] Remove separate movtf pattern – Use an iterator for all FP modes
Backport of [AArch64] Remove the hack for AARCH64_EXTRA_TUNE_ALL
Backport of [AArch64] TLSLE 1,2 and 3/N
Backport of [AArch64] Use default_elf_asm_named_section instead of special cased hook
Backport of [AArch64] Use default_elf_asm_named_section instead of special cased hook
Backport of [AArch64] Use logics_imm type for 2nd alternative of *and3nr_compare0
Backport of [AArch64] Use popcount_hwi instead of homebrew version
Backport of [Testsuite] Fix race on temp file in gfortran streamio_*.f90 tests
Backport of [Testsuite] Fix race on temp file in gfortran tests
Backport of [Testsuite] Fix typo in vcvt_f16.c testcase
Backport of [Testsuite] Adjust compiling options for gcc.target/arm/unsigned-float.c
Backport of [Testsuite] [AArch32] gcc.target/arm/pr67756.c: Fixed warnings
Backport of [Testsuite] [AArch64] 7/15 Add basic fp16 tests
Backport of [Testsuite] [AArch64] Adjust some arith+compare tests for potentially more aggressive if-conversion
Backport of [Testsuite] [AArch64] Make arm_align_max_stack_pwr.c and arm_align_max_pwr.c compile testcase, instead of execution
Backport of [Testsuite] [AArch64] Mark target_attr_1.c as compile-only
Backport of [testsuite] [AArch64] Remove divisions-to-produce-NaN from vdiv_f.c
Backport of [Testsuite] Add float16 lane_f16_indices tests
Backport of [Testsuite] auto-wipe dump files
Backport of [Testsuite] Clean up effective_target cache
Backport of [Testsuite] Clean up effective_target cache
Backport of [Testsuite] Fix order of dg-do and dg-require-effective-target directives
Backport of [testsuite] gcc.dg/builtins-20.c: Remove undefined behavior
Backport of [Testsuite] gcc.dg/tree-ssa/pr65447.c: Increase searching number
Backport of [Misc] add separate insn sched class for vector LDP & STP
Backport of [Misc] ccorrect ChangeLog dates+address
Backport of [Misc] fix typo in 223858 1/2
Backport of [Misc] fix typo in 223858 2/2
Backport of [Misc] Fix bigendian HFmode in native_interpret_real
Backport of [Misc] model load/store multiples properly in autoprefetcher scheduling
Backport of [Misc] Improve auto-increment addressing mode support in IVO by refactoring add candiate logic
Backport of [Misc] Improve bound information in loop niter analysis
Backport of [Misc] Improve conditional select ops on immediates
Backport of [Misc] Improve loop bound info by simplifying conversions in iv base
Backport of [Misc] IVOPS
Backport of [Misc] Look into unnecessary conversion when checking mult_op in get_shiftadd_cost
Backport of [Misc] Allow REG_EQUAL for ZERO_EXTRACT
Backport of [Misc] mark libstdc++ tests unsupported if they fail with relocation truncated
Backport of [Misc] Rerun loop-header-copying just before vectorization
Backport of [Misc] Allow PLUS+immediate expression in noce_try_store_flag_constants
Backport of [Doc] Clarify feature modifiers {no,}{fp,simd,crypto}

Feedback and Support

Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development.

Linaro Toolchain Development mailing list
Linaro Toolchain IRC channel on irc.freenode.net at #linaro-tcwg

Bug reports should be filed in bugzilla against GCC product:http://bugs.linaro.org/enter_bug.cgi?product=GCC
Interested in commercial support? inquire at Linaro support

¹ Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

² Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.