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The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.07 snapshot of the Linaro GCC 7 source package.

The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change.

For an explanation of the changes please see the following website:

This monthly snapshot1 is based on FSF GCC 7.1+svn250046 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2017.08 stable2 quarterly release.

Interesting changes in this GCC source package snapshot include:f

  • Updates to GCC 7.1+svn250046
  • Backport of [Bugfix] [AArch32] PR target/71778 ICE using non-constant argument to Neon intrinsic that requires constant arguments
  • Backport of [Bugfix] [AArch64] PR target/71663 aarch64 Vector initialization can be improved slightly
  • Backport of [AArch32] Enable FP16 vector arithmetic operations
  • Backport of [AArch32] Fix ARM bootstrap failure due to an odd warning
  • Backport of [AArch32] Modify idiv costs for Cortex-A53
  • Backport of [AArch64] Add combine pattern for storing lane zero of a vector
  • Backport of [AArch64] Add HF vector modes to lane-to-lane INS pattern
  • Backport of [AArch64] Add prefetch configuration to aarch64 backend
  • Backport of [AArch64] Adjust costs so udiv is preferred over sdiv when both are valid
  • Backport of [AArch64] Allow CMP+SHIFT when comparing with zero
  • Backport of [AArch64] Allow const0_rtx operand for atomic compare-exchange patterns
  • Backport of [AArch64] Emit tighter strong atomic compare-exchange loop when comparing against zero
  • Backport of [AArch64] Enable -fprefetch-loop-arrays at given optimization level
  • Backport of [AArch64] Fix -fstack-check with really big frames on aarch64
  • Backport of [AArch64] Fix subreg bug in scalar copysign
  • Backport of [AArch64] Peephole for SUBS
  • Backport of [AArch64] Simplify call, call_value, sibcall, sibcall_value patterns
  • Backport of [AArch64] Update prefetch tuning parameters for qdf24xx.
  • Backport of [AArch64] Use SUBS for parallel subtraction and comparison with immediate
  • Backport of [Misc] Add debug counter for loop array prefetching
  • Backport of [Misc] Improve debug output of loop data prefetching
  • Backport of [Cleanup] [AArch32] Complete legend for ARM register allocation in arm.h
  • Backport of [Cleanup] [AArch32] Fix comment for cmse_nonsecure_call_clear_caller_saved
  • Backport of [Cleanup] [AArch32] Fix typo in comment in arm_expand_prologue
  • Backport of [Testsuite] [AArch32] Add MOVT testing for ARMv8-M Baseline
  • Backport of [Testsuite] Add dg-require-stack-check
  • Backport of [Testsuite] Fix stack-check-1.c

Feedback and Support

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  • Linaro Toolchain Development mailing list
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  • Bug reports should be filed in bugzilla against GCC product:
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1 Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

2 Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.