This is a re-spin of the Linaro GCC 4.9 2015.04 source package snapshot
The re-spin of this snapshot includes a new configure-time option to enable by default a workaround for Cortex-A53 erratum number 843419 and options to explicitly disable or enable it during compilation.
Original release notes for GCC 4.9 2015.04 snapshot:
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.04 snapshot of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2015.04 is the first Linaro GCC source package snapshot in the 4.9 series. It is based on FSF GCC 4.9.3-pre+svn222035 and includes performance improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides stable1 quarterly releases and monthly snapshots2.
Interesting changes in this GCC source package snapshot include:
- Linaro bugzilla PR fixed: #415, #1382, #1391
- Updates to GCC 4.9.3-pre+svn222035
- Backport of instruction scheduler improvements
- Backport of [AArch64,Neon] Add patterns + builtins for vld234(q?)_lane_* intrinsics
- Backport of [AArch64] Implement fusion adrp+add/movk+movk
- Backport of [AArch32] Cortex-A17 support
- Backport of [AArch64] Fix __builtin_aarch64_absdi, must not fold to ABS_EXPR
- Backport of PR rtl-optimization/63917
- Backport of PR tree-optimization/62178 tree-ssa-loop-ivopts
- Backport of [AArch64] Add TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
- Backport of [AArch64] Simplify patterns for sshr_n_[us]64 intrinsic
- Backport of [AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsic
- Backport of [AArch32] Fix reservation pattern in cortex-a9-neon.md
- Backport of [AArch64] Don’t disparage add/sub in SIMD registers
- Backport of [AArch64] Add SIMD-reg variants of logical operators and/ior/xor/not
- Backport of [AArch64] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON
- Backport of [AArch32] Use Cortex-A17 tuning parameters for Cortex-A12
- Backport of [AArch32] Make CLZ_DEFINED_VALUE_AT_ZERO and CTZ_DEFINED_VALUE_AT_ZERO return 2.
- Backport of [AArch32] Minor optimization on thumb2 tail call
- Backport of [AArch64] Update APM/XGene-1
- Backport of [AArch64] Add a new scheduling description for the ARM Cortex-A57 processor
- Backport of [AArch64] Fix PR 64263: Do not try to split constants when destination is SIMD reg
- Backport of [AArch64] Add support for -mcpu=cortex-a72
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1Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.
2Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.