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application/x-tar gcc-linaro-5.2-2015.11-2-rc1.tar.xz 15-Jan-2018 17:40 69.6M open
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The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.11-2-rc1 stable Release-Candidate of the Linaro GCC 5 source package.

This Release-Candidate is based on FSF GCC 5.2.1-svn228499 and includes performance improvements and bug fixes backported from mainline GCC. This Release-Candidate is based on Linaro Snapshot GCC 5.2-2015.11 and includes the following performance improvements and bug fixes.

Changes in this stable GCC source package Release-Candidate include:

  • Updates merged from FSF GCC 5.2.1-svn228499
  • Backport of [Bugfix] [AArch64] PR target/63503 A57/FMA
  • Backport of [Testsuite] AdvSIMD intrinsics tests cleanup: remove useless expected values
  • Backport of [Doc] “move (Variable Attributes, Type Attributes) up”
  • Backport of [AArch32] 1-ARM/Thumb target attributes
  • Backport of [AArch32] fix date
  • Backport of [AArch32] 2-ARM/Thumb target attributes
  • Backport of [AArch32] 3-ARM/Thumb target attributes
  • Backport of [AArch64] Use conditional negate for abs
  • Backport of [AArch64] Removed unused SLOWMUL target flags
  • Backport of [Bugfix] [AArch32] PR target/65768
  • Backport of [Testsuite] [AArch64] Testsuite check for sqrt_insn
  • Backport of [Testsuite] Don’t specify “dg-do run” explicitly for vect test cases
  • Backport of [match-and-simplify] report error for invalid operator-lists
  • Backport of [match-and-simplify] fix incorrect code-gen in ‘for’ pattern
  • Backport of Fix ChangeLog
  • Backport of [match-and-simplify] reject expanding operator-list to implicit ‘for’
  • Backport of [AArch32] “attribute target (thumb,arm) [2.1/6]”
  • Backport of [Bugfix] [AArch32] “PR target/52144 attribute target (thumb,arm) [2.2/6]”
  • Backport of [AArch32] Fix ChangeLog
  • Backport of [Bugfix] Fix PR66168
  • Backport of [AArch64] Fix type of *one_cmpl3 pattern
  • Backport of [AArch64] Fuseable is not a word -> s/fuseable/fusible/g
  • Backport of [AArch32] Fuseable is not a word -> s/fuseable/fusible/g
  • Backport of Fuseable is not a word -> s/fuseable/fusible/g
  • Backport of [Bugfix] PR c/49551
  • Backport of [Bugfix] PR target/65768 Check cost of constants before propagating
  • Backport of [ifcvt Fix typo in comment
  • Backport of warn for empty struct -Wc++-compat
  • Backport of [AArch64] Always register fma_steering pass but gate it on the target option instead
  • Backport of The comparison in a compare exchange should not take place in VOIDmode
  • Backport of [Testsuite] gcc.target/arm/neon-reload-class.c: Remove movw and movt
  • Backport of [Testsuite] g++.dg/ext/pr57735.C should not run if the testsuite is explicitly passing -mfloat-abi=hard
  • Backport of [AArch32] Add ARM/thumb attribute target
  • Backport of [AArch32] Use dmb ish instead of dmb sy for ARM
  • Backport of [AArch32] Add ARM/thumb pragma target
  • Backport of fix typo
  • Backport of [AArch32] Restrict MAX_CONDITIONAL_EXECUTE when -mrestrict-it is in place
  • Backport of [AArch64] Change %ld to %wd for HOST_WIDE_INT parameter
  • Backport of [AArch64] movi type attribute confusion
  • Backport of [Testsuite] [AArch32] Fix gcc.target/arm/attr_thumb.c
  • Backport of [AArch32] Rename LOGICAL_OP_NON_SC to LOGICAL_OP_NON_SHORT_CIRCUIT
  • Backport of [Testsuite] [AArch32] Fix gcc.target/arm/thumb_ifcvt.c
  • Backport of [Testsuite] [AArch32] gcc.target/arm/pr65647.c should not add -mfloat-abi=soft
  • Backport of [AArch64] Add support for ARMv8.1 command line options
  • Backport of [Bugfix] [AArch32] “PR 66541, 52144 Fix ARM/thumb pragma target”
  • Backport of [Testsuite] New AdvSIMD tests (Multiple)
  • Backport of [AArch64] improve float/double 0.0 support
  • Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
  • Backport of [AArch64] Add ACLE predefined marcos: __ARM_ALIGN_MAX_PWR and __ARM_ALIGN_MAX_STACK_PWR
  • Backport of [Testsuite] Skip tests for inappropriate multilibs
  • Backport of [AArch64] Fix ICES with -mgeneral-regs-only / -march=…+nofp
  • Backport of [Doc] [AArch64] “Clarify feature modifiers {no,}{fp,simd,crypto}”
  • Backport of [AArch64] Fix another ICE with -mgeneral-regs-only
  • Backport of [Bugfix] [AArch32] Fix PR target/29693
  • Backport of [AArch32] Fix thinko in use of TARGET_UNIFIED_ASM
  • Backport of [AArch64] ¼ Define candidates for instruction fusion in a .def file
  • Backport of [AArch64] [2/4] Control the FMA steering pass in tuning structures rather than as core property
  • Backport of [AArch64] ¾ De-const-ify struct tune_params
  • Backport of [AArch64] [4/4] Add -moverride tuning command and wire it up for control of fusion and fma-steering
  • Backport of [AArch64] fix regrename pass to ensure renamings produce valid insns
  • Backport of [Bugfix] PR middle-end/64130
  • Backport of [AArch64] [armv8.1] Expand +rdma documentation. Small changes to march and mcpu text
  • Backport of [Testsuite] New AdvSIMD test
  • Backport of [Doc] [AArch64] Fix position of -moverride documentation
  • Backport of [Bugfix] [AArch32] PR 52144 Fix ARM/thumb attribute target
  • Backport of fix segfault in verify_flow_info() with -dx option
  • Backport of [Testsuite] [AArch32] Disable attr_thumb.c test when Thumb mode is not supported
  • Backport of Allow REG_EQUAL for ZERO_EXTRACT
  • Backport of [Bugfix] PR middle-end/66726
  • Backport of [Testsuite] [AArch32] Add -mfloat-abi=softfp to some xscale tests
  • Backport of Use cinc mnemonic for *csinc2_insn
  • Backport of [Testsuite] [AArch32] Do not override -mcpu in no-volatile-in-it.c
  • Backport of [Driver] Wrong C++ paths when configuring with “—with-sysroot=/”
  • Backport of [combine]½ Try to simplify before substituting
  • Backport of [simplify-rtx][2/2] Simplify – (y ? -x : x) -> (!y ? -x : x)
  • Backport of [Bugfix] [AArch64] PR63870 Neon error messages for vldN_lane/vstN_lane
  • Backport of [AArch64] typo fix in attribute for vst2_lane
  • Backport of Fix typo: Rename insn_reservation cortex_53_advsimd to cortex_a53_advsimd
  • Backport of ½ Allow REG_EQUAL for ZERO_EXTRACT
  • Backport of [2/2] Set REG_EQUAL
  • Backport of [AArch32] Correct spelling of references to ARMv6KZ
  • Backport of [AArch64] Improve spill code – swap order in shl pattern
  • Backport of [Bugfix] [AArch32] PR/63870 Add qualifier to check lane bounds in expand
  • Backport of [Bugfix] [AArch32] PR/63870 Add a __builtin_lane_check
  • Backport of [AArch64] Improve spill code – swap order in shr patterns
  • Backport of [Testsuite] [AArch64] vld1-vst1_1.c: Add missing float32×4_t case
  • Backport of [Bugfix] [AArch32] PR middle-end 64744/48470/43404
  • Backport of [Bugfix] PR tree-optimization/67043
  • Backport of [AArch64] 1/3 ARMv8.1 Use atomic compare-and-swap instructions when available
  • Backport of [AArch64] 2/3 ARMv8.1 Use the atomic compare-and-swap instructions when available
  • Backport of [AArch64] 3/3 ARMv8.1 Use the atomic compare-and-swap instructions when available
  • Backport of [Bugfix] Fix PR67280 and Linaro BZ #1765
  • Backport of [Bugfix] [AArch32] PR target/52144 target attributes Clean up arm_option_params_internals macro settings for attribute/pragma targets
  • Backport of [AArch32] Add TARGET_OPTION_PRINT
  • Backport of [AArch32] Fix static interworking call
  • Backport of [AArch64] 1/5 Use atomic instructions for swap and fetch-update operations
  • Backport of [AArch64] 2/5 Make BIC and other logical instructions available
  • Backport of [AArch64] 3/5 Add atomic load-operate instructions
  • Backport of [AArch64] 4/5 Use atomic load-operate instructions for fetch-update patterns
  • Backport of [AArch64] 5/5 Use atomic load-operate instructions for update-fetch patterns
  • Backport of [Testsuite] [AArch32] target attribute cleanup directives
  • Backport of [v8.1] [AArch64] —with-arch in config.gcc support “.”

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——

1 Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed.

2 Engineering source package releases are defined as releases where the compiler is only put through unit-testing and full validation is not performed.